Derive the VHDL code in multi-segment coding style for a register, next-state logic, and output logic. Make sure to perform type conversions if needed. library ieee; use ieee.std_logic_1164.all; entity even counter is port( clk, reset: in std_logic; max_val: out std_logic; q: out std_logic_vector (3 downto 0)); end even_counter; architecture multi_even_counter of even_counter is begin register