Design a four-bit shift register (not a universal shift register) with parallel load using D flip-flops. (See Figs. 6.2 and 6.3.) There are two control inputs: shift and load. When shift = 1, the content of the register is shifted toward Az by one position. New data are transferred into the register when load = 1 and shift = 0. If both control inputs are equal to O, the content of the register does not change. A D 4 PC D D D A C Clock Fig. 6.2 Four-bit register with parallel load SI Serial input D D D D so Serial output CLK Fig. 6.3 Four-bit shift register 6.7 Draw the logic diagram of a four-bit register with four D flip-flops and four 4 x 1 mul- tiplexers with mode selection inputs sı and . The register operates according to the following function table. (HDL-see Problem 6.35(e), ().) 51 50 Register Operation 0 0 No change Clock Fig. 6.2 Four-bit register with parallel load SI SO Serial input D D D D Serial output CLK Fig. 6.3 Four-bit shift register 6.7 Draw the logic diagram of a four-bit register with four D flip-flops and four 4 x 1 mul- tiplexers with mode selection inputs sį and so. The register operates according to the following function table. (HDL-see Problem 6.35(e), (O).) 51 50 0 1 0 1 0 0 1 1 Register Operation No change Complement the four outputs Clear register to 0 (synchronous with the clock) Load parallel data 6.27 Using JK flip-flops: (a) Design a counter with the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6. (b) Draw the logic diagram of the counter. 2